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SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
8 - Bit Micro-controller
with 4/8KB flash embedded
Product List
SM8951A/8952AL25, 25 MHz 4/8KB internal memory MCU SM8951A/8952AC25, 25 MHz 4/8KB internal memory MCU SM8951A/8952AC40, 40 MHz 4/8KB internal memory MCU
Features
Working voltage: 3.0V ~ 3.6V For L Version 4.5V ~ 5.5V For C Version General 8052 family compatible 12 clocks per machine cycle 4/8 KB internal flash memory
The SM8951A/8952A series product is an 8 - bit single chip micro controller with 4/8 KB flash embedded. It provides hardware features and a powerful instruction set, necessary to make it a versatile and cost effective controller for those applications demand up to 32 I/O pins or need up to 4/8 KB flash memory either for program or for data or mixed. To program the flash block, a commercial programmer is capable to do it.
Ordering Information
yywwv SM8951A/8952Aihhk
yy: year, ww:week v: version identifier {, A, B,...} i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table}
Postfix P J Q
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D R AF T, D C O O N NF O T ID C EN O PY TIA L
128/256 bytes data RAM Four 8-bit I/O ports 2/3 16 bit timers/counters Full duplex serial channel Bit operation instruction Page free jumps 8-bit unsigned division BCD arithmetic 8-bit unsigned multiply Direct addressing Nested interrupt A serial I/O port Indirect addressing Two priority level interrupt Power save modes: Idle mode and power down mode Code protection function One watch dog timer (WDT)
Package 40L PDIP 44L PLCC 44L QFP Pin/Pad Configuration page 2 page 2 page 2 Dimension page 13 page 14 page 15
Description
Low EMI (inhibit ALE)
Taiwan 4F, No. 1 Creation Road 1, Science-based Industrial Park, Hsinchu, Taiwan 30077 TEL: 886-3-579-2926 886-3-579-2988 FAX: 886-3-579-2960 886-3-578-0493
1/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
Pin Configurations
T2EX/P1.1 T2/P1.0 NC VDD P0.0/AD0 P0.1/AD1
T2EX/P1.1 T2/P1.0
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
D R AF T, D C O O N NF O T ID C EN O PY TIA L
6 5
P1.4
P1.3 P1.2
4
3
2
1 44 43 42 41 40
P1.5
7
39
P0.4/AD4 P0.5/AD5 P0.6/AD6 #EA/VPP NC ALE #PSEN
P1.6 P1.7 RES RXD/P3.0 NC TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5
8
38
P1.5 P1.6
9
37
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
P0.2/AD2 P0.3/AD3
P1.4
P1.3
P1.2
NC VDD
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA/VPP NC ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13
10 11 12 13
SM8951A/8952A ihhJ 44L PLCC
36
P0.7/AD7
35
34
P1.7 RES RXD/P3.0
33
14 (Top View) 15 16 17 18 19 20 21 22 23 24 25 26 27 28
32
NC TXD/P3.1 #INT0/P3.2
SM8951A/8952A ihhQ 44L QFP (Top View)
31
30
P2.7/A15 P2.6/A14 P2.5/A13
29
#INT1/P3.3 T0/P3.4 T1/P3.5
10 11
12 13 14 15 16 17 18 19 20 21 22
#WR/P3.6
#RD/P3.7 XTAL2 XTAL1 VSS
P2.2/A10
P2.3/A11
P2.4/A12
P2.0/A8
P2.1/A9
NC
#WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS
P2.3/A11
T2/P1.0
1 2
40 39
VDD
T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA/VPP ALE
3 4 5
38
37
36
6 7
35 34
8
33
RES RXD/P3.0 TXD/P3.1
9
32
10 11
31
30
#INT/P3.2
12
13
29
#PSEN
#INT1/P3.3 T0/P3.4 T1/P3.5 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS
28 27 26 25 24 23 22 21
P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
14 15 16 17 18 19 20
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/17
Preliminary Ver 0.2
P2.2/A10
PID 8951A/8952A 09/02
P2.4/A12
NC
P2.0/A8
P2.1/A9
SM8951A/8952A ihhP
40L PDIP (Top View)
SyncMOS Technologies Inc.
September 2002 Block Diagram
Stack Pointer
Preliminary
SM8951A/8952A
Timer 2
Timer 1
Timer 0
Decoder & Register
128/256 bytes RAM
RES
Vdd Vss
XTAL2 XTAL1 #EA ALE #PSEN
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D R AF T, D C O O N NF O T ID C EN O PY TIA L
WDT
Reset Circuit to pertinent blocks Acc Power Circuit to whole chip Buffer2 Buffer1 Interrupt Circuit to pertinent blocks ALU PSW to whole system Timing Generator Instruction Register Port 0 Latch Port 1 Latch Port 2 Latch Port 3 Latch Port 0 Driver & Mux 8 Port 2 Port 3 Driver & Mux Driver & Mux Driver & Mux 8 8 8 Port 1
Buffer
DPTR
PC Incrementer
Program Counter
Register
4/8 K bytes
Flash Memory
3/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002 Pin Descriptions
40L PDIP Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44L 44L QFP PLCC Symbol Pin# Pin# 40 2 T2/P1.0 41 3 T2EX/P1.1 42 4 P1.2 43 5 P1.3 44 6 P1.4 1 7 P1.5 2 8 P1.6 3 9 P1.7 4 10 RES 5 11 RXD/P3.0 7 13 TXD/P3.1 8 14 #INT0/P3.2 9 15 #INT1/P3.3 10 16 T0/P3.4 11 17 T1/P3.5 12 18 #WR/P3.6 13 19 #RD/P3.7 14 20 XTAL2 15 21 XTAL1 16 22 VSS 18 24 P2.0/A8 19 25 P2.1/A9 20 26 P2.2/A10 21 27 P2.3/A11 22 28 P2.4/A12 23 29 P2.5/A13 24 30 P2.6/A14 25 31 P2.7/A15 26 32 #PSEN 27 33 ALE 29 35 #EA/VPP 30 36 P0.7/AD7 31 37 P0.6/AD6 32 38 P0.5/AD5 33 39 P0.4/AD4 34 40 P0.3/AD3 35 41 P0.2/AD2 36 42 P0.1/AD1 37 43 P0.0/AD0 38 44 VDD I/O Active i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i Names
Preliminary
SM8951A/8952A
H
L/ L/ -
L/ L/ -
L L
i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o
timer 2 clock out & bit 0 of port 1 timer 2 control & bit 1 of port 1 bit 2 of port 1 bit 3 of port 1 bit 4 of port 1 bit 5 of port 1 bit 6 of port 1 bit 7 of port 1 Reset Receive data & bit 0 of port 3 Transmit data & bit 1 of port 3 low true interrupt 0 & bit 2 of port 3 low true interrupt 1 & bit 3 of port 3 Timer 0 & bit 4 of port 3 Timer 1 & bit 5 of port 3 external memory write & bit 6 of port 3 external memory read & bit 7 of port 3 Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of external memory address bit 1 of port 2 & bit 9 of external memory address bit 2 of port 2 & bit 10 of external memory address bit 3 of port 2 & bit 11 of external memory address bit 4 of port 2 & bit 12 of external memory address bit 5 of port 2 & bit 13 of external memory address bit 6 of port 2 & bit 14 of external memory address bit 7 of port 2 & bit 15 of external memory address program storage enable address latch enable external access & VPP bit 7 of port 0 & data/address bit 7 of external memory bit 6 of port 0 & data/address bit 6 of external memory bit 5 of port 0 & data/address bit 5 of external memory bit 4 of port 0 & data/address bit 4 of external memory bit 3 of port 0 & data/address bit 3 of external memory bit 2 of port 0 & data/address bit 2 of external memory bit 1 of port 0 & data/address bit 1 of external memory bit 0 of port 0 & data/address bit 0 of external memory Drive Voltage, +5 Vcc
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D R AF T, D C O O N NF O T ID C EN O PY TIA L
4/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
SFR Memory MAP
$F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80
B ACC
$FF $F7 $EF $E7 $DF $D7 $CF
SCONF
D R AF T, D C O O N NF O T ID C EN O PY TIA L
PSW T2CON IP RC2L RC2H TL2 TH2 P3 IE P2 P1 P0 SCON TCON SBUF TMOD SP TL0 TL1 TH0 TH1 DPL DPH (Reserved)
5/17 Preliminary Ver 0.2
$C7 $BF $B7 $AF $A7 $9F $97 $8F $87
WDTC
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8951A/8952A
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. The SM8951A/8952A WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8951A8952A been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
WDTE Reset value 0 MSB WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS2 ~ PS0 : clock source divider bit PS [2:0] 000 001 010 011 100 101 110 111 Unused * CLEAR 0 Unused * Unused * PS2 0 PS1 0 PS0 0 LSB
Watch Dog Timer Register - System Control Register (SCONF, $BF)
WDR 0 Unused * Unused * Unused * Unused *
D R AF T, D C O O N NF O T ID C EN O PY TIA L
Divider (OSC in) 8 16 32 Time Period (ms) @40MHZ 13.1 26.21 52.42 64 104.8 128 256 209.71 419.43 512 838.86 1024 1677.72 Unused * *
MSB 6/17 Preliminary Ver 0.2
Unused
ALEI 0
LSB
Reset value
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1 ALEI : ALE output inhibit bit, to reduce EMI The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM8951A/8952A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is no external program memory or no external data RAM in the system.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
Operating Conditions
Symbol TA TS VCC5 VCC3 Description Operating temperature Storage temperature Supply voltage Min. 0 -55 4.5 Typ. 25 25 5.0 Max. 70 155 5.5 16 40 Unit.
oC oC
Remarks Ambient temperature under bias
Fosc 16
Fosc 25 Fosc 40
DC Characteristics
Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC
(16/25/40MHz, typical operating conditions, valid for SM8951A/8952A version series)
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D R AF T, D C O O N NF O T ID C EN O PY TIA L
Supply voltage 3 3.3 3.6 V For L Version Oscillator Frequency 3.0 16 40 Oscillator Frequency 3.0 25 25 Oscillator Frequency 3.0 MHz For 5V application
V
For C Version
MHz For 5V, 3.3V application MHz For 5V, 3.3V application
Parameter
Valid
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage
port 0,1,2,3,4,#EA RES, XTAL1 port 0,1,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 1,2,3,4 port 0
Min. -0.5 0 2.0 70%Vcc
Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45
Unit
Test Conditions
port 1,2,3,4,ALE,#PSEN port 1,2,3,4 port 1,2,3,4 port 0, #EA RES Vdd
2.4 90%Vcc 2.4 90%Vcc
Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current
50
V V V V V V V V V V uA -75 uA -650 + 10 uA 300 Kohm 10 pF 15 mA 10 mA 7 mA 10 mA mA 7 4.5 mA 10 uA
IOL=3.2mA IOL=1.6mA IOH=-800uA (only for VCC =5V) IOH=-80uA IOH=-60uA (only for VCC =5 V) IOH=-10uA Vin=0.45V Vin=2.0V 0.45V7/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002 AC Characteristics
Preliminary
SM8951A/8952A
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF) Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T, TCLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time clock period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT fosc=16MHz Min. Typ. Max 115 43 53 240 53 173 177 0 87 292 10 365 365 302 0 145 590 542 178 197 230 403 38 73 53 Variable fosc Unit Min. Typ. Max 2xT - 10 nS T - 20 nS T - 10 nS 4xT - 10 nS T - 10 nS 3xT - 15 nS 3xT - 10 nS 0 nS T + 25 nS 5xT - 20 nS 10 nS 6xT - 10 nS 6xT - 10 nS 5xT - 10 nS 0 nS 2xT + 20 nS 8xT - 10 nS 9xT - 20 nS 3xT - 10 3xT + 10 nS 4xT - 20 nS 7xT - 35 nS T - 25 nS T + 10 nS 5 nS 72 T -10 T + 10 nS nS nS nS nS 1/fosc nS Remarks
ICC Active mode test circuit Vcc
D R AF T, D C O O N NF O T ID C EN O PY TIA L
63 ICC Idle mode test circuit ICC Vcc VCC RST SM8951A/ SM8952A PO EA 8 RST SM8951A/ SM8952A (NC) Clock Signal XTAL2 XTAL1 VSS XTAL2 XTAL1 VSS 8/17
ICC VCC PO EA 8
Vcc
(NC) Clock Signal
Specifications subject to change without notice,contact your sales representatives for the most recent information.
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002 Application Reference Valid for SM8951A/8952A
X'tal C1 C2 R 3MHz 30 p 30 p open 6MHz 30 p 30 p open 9MHz 30 p 30 p open 12MHz 30 p 30 p open
Preliminary
SM8951A/8952A
XI X'tal
NOTE: Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics.
Data Memory Read Cycle Timing
T12 T1 T2 T3 T4
D R AF T, D C O O N NF O T ID C EN O PY TIA L
X'tal C1 C2 R 16MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K 33MHz 10 pF 10 pF 6.8K 40MHz 5 pF 5 pF 4.7K
R X2 C1 C2
SM8951A/8952A
User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
1
2
ALE
#PSEN
#RD
5
7
3
PORT2
ADDRESS A15 - A8
3
4 Float
6 DATA in
8 Float ADDRESS or Float
PORT0
INST in Float
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002 Program Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8
Preliminary
SM8951A/8952A
T9
T10
T11
T12
T1
T2
OSC ALE
1
2
#PSEN
#RD,#WR
PORT2
PORT0
Data Memory Write Cycle Timing
T12 T1 T2 T3
D R AF T, D C O O N NF O T ID C EN O PY TIA L
5 7 3 ADDRESS A15 - A8 ADDRESS A15 - A8 3 4 6 8 Float A7 - A0 Float INST in Float A7 - A0 Float INST in T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 1 5 6
2
Float
T2
T3
OSC
ALE
#PSEN
#WR
PORT2
2
ADDRESS A15 - A8
3 DATA OUT
4 ADDRESS or Float
PORT0
INST
Float
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1 inputs P0,P1
sampled
inputs P2,P3 Output by Mov Px,Src
RxD at Serial Port Shift Clock (Mode 0)
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
Vdd-0.5V
70%Vdd
Tm.I
#PSEN ALE
PORT 0
PORT 2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D R AF T, D C O O N NF O T ID C EN O PY TIA L
sampled current data next data sampled TCLCL
0.45V
20%Vdd-0.1V
TCHCL
TCLCX
TCHCX
TCLCH
External Program Memory Read Cycle
TPLPH
TLHLL
TLLPL
TPXIZ
TAVLL
TLLAX
TPLAZ
TPLIV
TPXIX
A0 - A7
Instruction. IN
A0 - A7
TAVIV A8 - A15 A8 - A15
11/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002 Tm.II External Data Memory Read Cycle
Preliminary
SM8951A/8952A
#PSEN
TYHLH
ALE
#RD
D R AF T, D C O O N NF O T ID C EN O PY TIA L
TLLDV TLLYL TRLRH TAVLL TLLAX TRLAZ TRLDV TRHDZ TRHDX A0 - A7 from Ri or DPL TAVYL TAVDV DATA IN P2.0 - P2.7 or A8 - A15 from DPH TYHLH TLHLL TLLYL TWLWH TAVLL TLLAX
TQVWX
PORT 0
A0 - A7 from PCL
INSTRL IN
PORT 2
A8 - A15 from PCH
Tm.III External Data Memory Write Cycle
#PSEN
ALE
#WR
TQVWH
TWHQX
PORT 0
A0-A7 from Ri or DPL
DATA OUT
A0-A7 From PCL
INSTRL IN
TAVYL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
40L 600mil PDIP Information
E S
D R AF T, D C O O N NF O T ID C EN O PY TIA L
E1 A2 A L e1 B1 B eA Symbol A A1 A2 B B1 C D E E1 e1 L a eA S Dimension in inch minimal/maximal - / 0.210 0.010 / 0.150 / 0.160 0.016 / 0.022 0.048 / 0.054 0.008 / 0.014 - / 2.070 0.590 / 0.610 0.540 / 0.552 0.090 / 0.110 0.120 / 0.140 0 / 15 0.630 / 0.670 - / 0.090 13/17
D
A1
C
a
Note: 1. Dimension D Max & include mold flash or tie bar burrs. 2. Dimension E1 does not include inter lead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dam bar protrusion/ infusion. 5. Controlling dimension is inch. 6. General appearance spec. should base on final visual inspection spec.
Dimension in mm minimal/maximal - / 5.33 0.25 / 3.81 / 4.06 0.41 / 0.56 1.22 / 1.37 0.20 / 0.36 - / 52.58 14.99 / 15.49 13.72 / 14.02 2.29 / 2.79 3.05 / 3.56 0 / 15 16.00 / 17.02 - / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002 44L Plastic Chip Carrier (PLCC)
6 7
Preliminary
SM8951A/8952A
L
D R AF T, D C O O N NF O T ID C EN O PY TIA L
E HE y D HD A2 A1 A C b1 e b GD Symbol A A1 A2 b1 b C D E e GD GE HD HE L
GE
Note:
1. Dimension D & E does not include inter lead flash. intrusion. 3. Controlling dimension: Inch
2. Dimension b1 does not include dam bar protrusion/
4. General appearance spec. should base on final visual inspection spec.
y
Dimension in inch minimal/maximal - / 0.185 0.020 / 0.145 / 0.155 0.026 / 0.032 0.016 / 0.022 0.008 / 0.014 0.648 / 0.658 0.648 / 0.658 0.050 BSC 0.590 / 0.630 0.590 / 0.630 0.680 / 0.700 0.680 / 0.700 0.090 / 0.110 - / 0.004 /
Dimension in mm minimal/maximal - / 4.70 0.51 / 3.68 / 3.94 0.66 / 0.81 0.41 / 0.56 0.20 / 0.36 16.46 / 16.71 16.46 / 16.71 1.27 BSC 14.99 / 16.00 14.99 / 16.00 17.27 / 17.78 17.27 / 17.78 2.29 / 2.79 - / 0.10 /
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/17
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
44L Plastic Quad Flat Package
C L S e L1 2 R1
D R AF T, D C O O N NF O T ID C EN O PY TIA L
D2 D1 D b A2 3 A1 E2 E1 E A e1 seating plane e C Symbol A A1 A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 1 2 3 C Dimension in Inch minimal/maximal - / 0.100 0.006 / 0.014 0.071 / 0.087 0.012 / 0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005 / 0.005 / 0.012 0.008 / 0 / 7 0 / 10 REF 7 REF 0.004 15/17
Gage Plane 0.25 mm
R2
Note:
Dimension D1 and E1 do not include mold protrusion. Allowance protrusion is 0.25mm per side. and are determined datum plane. Dimension D1 and E1 do include mold mismatch
Dimension b does not include dam bar protrusion.
Allowance dam bar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material radius or the lead foot. condition. Dam bar cannot be located on the lower
Dimension in mm minimal/maximal - / 2.55 0.15 / 0.35 1.80 / 2.20 0.30 / 0.45 0.09 / 0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73 / 1.03 1.60 0.13 / 0.13 / 0.30 0.20 / as left as left as left as left 0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
Preliminary Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
eMCU writer list
Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number LabTool - 48 (1 * 1) LabTool - 848 (1*8)
Caprilion P.O. Box 461 KaoHsiung, Taiwan, ROC Web site: http://www.market.net.tw/ ~ cap/ Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang Rd., Nei Hu, Taipei, Taiwan, ROC. Web site: http://www.hilosystems.com.tw
Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei Hsien, Taiwan, ROC Web site: http://www.leap.com.tw
Xeltek Electronic Co., Ltd 338 Hongwu Road, Nanjing, China 210002 Web site: http://www.xeltek-cn.com
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D R AF T, D C O O N NF O T ID C EN O PY TIA L
Tel:07-3865061 Fax:07-3865421 E-mail: cap@market.net.tw UNIV2000 Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw All - 11 (1*1) Gang - 08 (1*8) Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw ChipStation (1*1) SU - 2000 (1*8) Tel:+86-25-4408399, 4543153-206 E-mail: xelclw@jlonline.com, xelgbw@jlonline.com 16/17
Superpro/2000 (1*1) Superpro/680 (1*1) Superpro/280 (1*1) Superpro/L+(1*1)
Preliminary Ver 0.2
PID 8951A/8952A 09/02
1 I/uIO
TEL:025-4408399 http://www.xeltek.com.cn
SUPERPRO/8000 SUPERPRO/2000 SUPERPRO/680 SUPERPRO/280 SUPERPRO/L+ RF-1848 RF-1800 RF-810 RF-510 WH800AP/BP WH500AU/BU WH500AP/BP WH500A/B WH200A/B
2
Eo*E
TEL:010-62574562 http://www.whkj.com.cn
3
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TEL:010-62634711 http://www.runfei.com.cn
EIAAe1/4IaOIE3/4 EIEIiAOA 300AIiAOoA 021648538162816 OEa 200233

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